1. Field of the Invention
The present invention relates to a semiconductor testing system, and a testing method. In particular, the invention relates to a semiconductor testing system, and a testing method, which are used for detecting a stuck-at fault in a semiconductor device.
2. Description of Related Art
In recent years, semiconductor devices such as LSI (Large Scale Integration) have proceeded toward large-scale circuits, complicated functions, and finer design rules. In the LSI, a stuck-at fault that the circuit logic value is stuck at 1 or 0 occurs due to short-circuited lines in the LSI or breakdown of elements. For detecting the stuck-at fault, the LSI with a built-in fault detecting element has been hitherto used. Japanese Unexamined Patent Publication No. 2002-139546 (Related Art 1) discloses a technique of detecting the stuck-at fault with the built-in element.
FIG. 4 is a block diagram of a semiconductor device 100 as disclosed in Japanese Unexamined Patent Publication No. 2002-139546. As shown in FIG. 4, the semiconductor device 100 includes a 3-state buffer 112, and a scan flip-flop (SFF) 113. The 3-state buffer 112 is connected with a logic circuit 110 embedded in the semiconductor device 100 to transmit/receive data through a data line 115. Further, the 3-state buffer 112 receives a control signal from the logic circuit 110 through a control line 114. Then, an output mode and a high impedance mode are switched from each other in accordance with the control signal. The scan flip-flop (SFF) 113 is connected with the control line 114. The scan flip-flop 113 memorizes a stuck-at fault that occurs in the logic circuit connected with the control line 114 or on the control line 114.
How to detect a stuck-at fault that occurs in the semiconductor device 100 is described next. Assuming that a stuck-at fault occurs on the data line 115 connected with the 3-state buffer 112 or on an input/output line 116, a test pattern for detecting the stuck-at fault is input to the logic circuit 110, and a level of a signal output to an input/output terminal 118 to thereby detect the stuck-at fault. Assuming that a stuck-at fault occurs in the control line 114, a test pattern for detecting the stuck-at fault is input to the logic circuit 110, and a signal level of the control line 114 is memorized with the scan flip-flop 113 to obtain an output of the scan flip-flop 113 to detect the stuck-at fault.
Further, as another fault mode of the LSI, there is a transmission fault. The transmission fault is such that in a circuit capable of outputting high impedance in a 3-state buffer, for example, an output terminal is shifted from a high level or a low level to a high impedance with a considerable delay. Upon detecting the transmission fault, the input/output terminal of the 3-state buffer is connected with an element such as a resistor, a period up to the shift of the output terminal from a high level or low level to a high impedance is measured. In general, this resistive element is embedded in the LSI. Japanese Unexamined Patent Publication Nos. 2000-55989 and 2000-338191 disclose a technique of detecting a transmission fault with this built-in element.
However, recent LSI circuits are enlarged, and a number of elements for detecting a stuck-at fault should be embedded in the LSI. This results in a problem that a chip area increases and it is difficult to wire elements.
Further, in the case of detecting a stuck-at fault with the scan flip-flop in the conventional semiconductor device, a test pattern for outputting stored information about the stuck-at fault is required. Therefore, a long test pattern should be generated. Further, there arises a problem in that the long test pattern increases a test period.